Unit AHCI

Description

Drivers->Storage->AHCI - AHCI SATA Driver.

Overview

Classes, Interfaces, Objects and Records

Name Description
Record TSataDevice  

Functions and Procedures

procedure init();
procedure check_ports(controller : uint8);
procedure enable_cmd(port : uint8);
procedure disable_cmd(port : uint8);
procedure port_rebase(port : uint8);
function load(ptr:void): boolean;
function read(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
function write(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
function find_cmd_slot(port : uint8) : uint32;

Types

TFIS_Type = (...);
PFIS_REG_H2D = ˆTFIS_REG_H2D;
TFIS_REG_H2D = bitpacked record fis_type : uint8; port_mult : UBit4; rsv0 : UBit3; coc : boolean; command : uint8; feature_low : uint8; lba0 : uint8; lba1 : uint8; lba2 : uint8; device : uint8; lba3 : uint8; lba4 : uint8; lba5 : uint8; feature_high : uint8; count_low : uint8; count_high : uint8; icc : uint8; control : uint8; rsvl : uint32; end;
TFIS_REG_D2H = bitpacked record fis_type : uint8; port_mult : UBit4; rsv0 : UBit2; i : boolean; rsvl : boolean; status : uint8; error : uint8; lba0 : uint8; lba1 : uint8; lba2 : uint8; device : uint8; lba3 : uint8; lba4 : uint8; lba5 : uint8; rsv2 : uint8; count_low : uint8; count_high : uint8; rsv3 : uint16; rsv4 : uint32; end;
TFIS_Data = bitpacked record fis_type : uint8; port_mult : UBit4; rsv0 : UBit4; rsv1 : uint16; data : ˆuint32; end;
TFIS_PIO_Setup = bitpacked record fis_type : uint8; pmport : UBit4; rsv0 : boolean; d : boolean; i : boolean; rsv1 : boolean; status : uint8; error : uint8; lba0 : uint8; lba1 : uint8; lba2 : uint8; device : uint8; lba3 : uint8; lba4 : uint8; lba5 : uint8; rsv2 : uint8; countl : uint8; counth : uint8; rsv3 : uint8; e_status : uint8; tc : uint16; rsv4 : uint16; end;
PHBA_PORT = ˆTHBA_PORT;
THBA_PORT = bitpacked record clb : uint32; clbu : uint32; fb : uint32; fbu : uint32; istat : uint32; ie : uint32; cmd : uint32; rsv0 : uint32; tfd : uint32; sig : uint32; ssts : uint32; sctl : uint32; serr : uint32; sact : uint32; ci : uint32; sntf : uint32; fbs : uint32; rsv1 : array[0..11] of uint32; vendor : array[0..4] of uint32; end;
THBA_MEM = bitpacked record cap : uint32; global_host_control : uint32; interrupt_status : uint32; port_implemented : uint32; version : uint32; ccc_control : uint32; ccc_ports : uint32; em_location : uint32; em_Control : uint32; hcap2 : uint32; bohc : uint32; rsv0 : array[0..210] of boolean; ports : array[0..31] of THBA_Port; end;
PHBA = ˆTHBA_MEM;
PCMDHeader = ˆ TCommand_Header;
TCommand_Header = bitpacked record cfl : ubit5; a : boolean; w : boolean; p : boolean; r : boolean; b : boolean; c : boolean; rsv0 : boolean; pmp : ubit4; PRDTL : uint16; PRDTBC : uint32; CTBA : uint32; CTBAU : uint32; rsv1 : array[0..3] of uint32; end;
TPRD_Entry = bitpacked record data_base_address : uint32; data_bade_address_U : uint32; rsv0 : uint32; data_byte_count : ubit22; rsv1 : ubit9; interrupt_oc : boolean; end;
PCommand_Table = ˆTCommand_Table;
TCommand_Table = bitpacked record cfis : array[0..64] of uint8; acmd : array[0..16] of uint8; rsv : array[0..48] of uint8; prdt : array[0..7] of TPRD_Entry; end;

Variables

AHCI_BASE: uint32 = $400000;
ahciControllers: array[0.16] of PuInt32;
ahciControllerCount: uint8 = 0;
hba: array[0..16] of PHBA;
sataDevices: array[0..127] of TSataDevice;
sataDeviceCount: uint8;

Description

Functions and Procedures

procedure init();
 
procedure check_ports(controller : uint8);
 
procedure enable_cmd(port : uint8);
 
procedure disable_cmd(port : uint8);
 
procedure port_rebase(port : uint8);
 
function load(ptr:void): boolean;
 
function read(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
 
function write(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
 
function find_cmd_slot(port : uint8) : uint32;
 

Types

TFIS_Type = (...);

Struct hell

Values
  • REG_H2D = $27
  • REG_D2H = $34
  • DMA_ACT = $39
  • DMA_SETUP = $41
  • DATA = $46
  • BIST = $58
  • PIO_SETUP = $5F
  • DEV_BITS = $A0
PFIS_REG_H2D = ˆTFIS_REG_H2D;
 
TFIS_REG_H2D = bitpacked record fis_type : uint8; port_mult : UBit4; rsv0 : UBit3; coc : boolean; command : uint8; feature_low : uint8; lba0 : uint8; lba1 : uint8; lba2 : uint8; device : uint8; lba3 : uint8; lba4 : uint8; lba5 : uint8; feature_high : uint8; count_low : uint8; count_high : uint8; icc : uint8; control : uint8; rsvl : uint32; end;
 
TFIS_REG_D2H = bitpacked record fis_type : uint8; port_mult : UBit4; rsv0 : UBit2; i : boolean; rsvl : boolean; status : uint8; error : uint8; lba0 : uint8; lba1 : uint8; lba2 : uint8; device : uint8; lba3 : uint8; lba4 : uint8; lba5 : uint8; rsv2 : uint8; count_low : uint8; count_high : uint8; rsv3 : uint16; rsv4 : uint32; end;
 
TFIS_Data = bitpacked record fis_type : uint8; port_mult : UBit4; rsv0 : UBit4; rsv1 : uint16; data : ˆuint32; end;
 
TFIS_PIO_Setup = bitpacked record fis_type : uint8; pmport : UBit4; rsv0 : boolean; d : boolean; i : boolean; rsv1 : boolean; status : uint8; error : uint8; lba0 : uint8; lba1 : uint8; lba2 : uint8; device : uint8; lba3 : uint8; lba4 : uint8; lba5 : uint8; rsv2 : uint8; countl : uint8; counth : uint8; rsv3 : uint8; e_status : uint8; tc : uint16; rsv4 : uint16; end;
 
PHBA_PORT = ˆTHBA_PORT;

TFIS_DMA_Setup = bitpacked record end; THBA_Memory = bitpacked record end; THBA_Port = bitpacked record end; THBA_FIS = bitpacked record end;

THBA_PORT = bitpacked record clb : uint32; clbu : uint32; fb : uint32; fbu : uint32; istat : uint32; ie : uint32; cmd : uint32; rsv0 : uint32; tfd : uint32; sig : uint32; ssts : uint32; sctl : uint32; serr : uint32; sact : uint32; ci : uint32; sntf : uint32; fbs : uint32; rsv1 : array[0..11] of uint32; vendor : array[0..4] of uint32; end;
 
THBA_MEM = bitpacked record cap : uint32; global_host_control : uint32; interrupt_status : uint32; port_implemented : uint32; version : uint32; ccc_control : uint32; ccc_ports : uint32; em_location : uint32; em_Control : uint32; hcap2 : uint32; bohc : uint32; rsv0 : array[0..210] of boolean; ports : array[0..31] of THBA_Port; end;
 
PHBA = ˆTHBA_MEM;

0 4 8 c 10 14 18 1c 20 24 28

PCMDHeader = ˆ TCommand_Header;
 
TCommand_Header = bitpacked record cfl : ubit5; a : boolean; w : boolean; p : boolean; r : boolean; b : boolean; c : boolean; rsv0 : boolean; pmp : ubit4; PRDTL : uint16; PRDTBC : uint32; CTBA : uint32; CTBAU : uint32; rsv1 : array[0..3] of uint32; end;
 
TPRD_Entry = bitpacked record data_base_address : uint32; data_bade_address_U : uint32; rsv0 : uint32; data_byte_count : ubit22; rsv1 : ubit9; interrupt_oc : boolean; end;
 
PCommand_Table = ˆTCommand_Table;
 
TCommand_Table = bitpacked record cfis : array[0..64] of uint8; acmd : array[0..16] of uint8; rsv : array[0..48] of uint8; prdt : array[0..7] of TPRD_Entry; end;
 

Variables

AHCI_BASE: uint32 = $400000;

constants SATA_SIG_ATA := $101; SATA_SIG_ATAPI := $EB140101; STA_SIG_SEMB := $C33C0101; STAT_SIG_PM := $96690101;

ahciControllers: array[0.16] of PuInt32;

irrelivent other

ahciControllerCount: uint8 = 0;
 
hba: array[0..16] of PHBA;
 
sataDevices: array[0..127] of TSataDevice;
 
sataDeviceCount: uint8;
 

Author


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